1. Field of the Invention
The present invention relates to a DC/DC converter.
2. Description of the Related Art
Various kinds of consumer electronics devices such as TVs, refrigerators, etc., are each configured to operate receiving commercial AC electric power from an external circuit. Also, electronic devices such as laptop computers, cellular phone terminals, and PDAs (Personal Digital Assistants) are each configured to operate using commercial AC electric power, and/or to be capable of charging a built-in battery using such commercial AC electric power. Such consumer electronics devices and electronic devices (which will collectively be referred to as “electronic devices” hereafter) each include a built-in power supply apparatus (inverter) configured to perform AC/DC conversion of commercial AC voltage. Alternatively, such an inverter is configured as a built-in component included within an external power supply adapter (AC adapter) for such an electronic device.
Related techniques are disclosed in Japanese Patent Application Laid-Open No. H09-098571, and Japanese Patent Application Laid-Open No. H02-211055, for example.
FIG. 1 is a block diagram showing an inverter investigated by the present inventor. An inverter 1r mainly includes a fuse 2, an input capacitor Ci, a filter 4, a diode rectifier circuit 6, a smoothing capacitor Cs, and a DC/DC converter 10r. 
The commercial AC voltage VAC is input to the filter 4 via the fuse 2 and the input capacitor Ci. The filter 4 is configured to remove noise included in the commercial AC voltage VAC. The diode rectifier circuit 6 is configured as a diode bridge circuit configured to perform full-wave rectification of the commercial AC voltage VAC. The output voltage of the diode rectifier circuit 6 is smoothed by the smoothing capacitor Cs, thereby generating a converted DC voltage VH.
The insulated DC/DC converter 10r is configured to receive the DC voltage VH via an input terminal P1, to step down the DC voltage VH thus received, and to supply an output voltage VOUT stabilized to the target value to a load (not shown) connected to an output terminal P2.
The DC/DC converter 10r includes a control circuit 100r, an output circuit 200, and a feedback circuit 210. The output circuit 200 includes a transformer T1, a first diode D1, a first output capacitor CM, a switching transistor M1, and a detection resistor RS. The output circuit 200 has a typical topology, and accordingly, detailed description thereof will be omitted.
An output terminal (OUT terminal) of the control circuit 100r is connected to the gate of the switching transistor M1 via a resistor Rg. The control circuit 100r is configured to perform switching of the switching transistor M1 so as to step down the input voltage VH, thereby generating the output voltage VOUT. Furthermore, by adjusting the duty ratio of the switching operation of the switching transistor M1, the control circuit 100r is configured to stabilize the output voltage VOUT to a target value, and to control a coil current ILp that flows through a primary winding W1 of the transformer T1.
The detection resistor RS is arranged in series with the primary winding W1 of the transformer T1 and the switching transistor M1. A voltage drop (detection voltage) VCS, which is proportional to the current ILp that flows through the primary winding W1 and the switching transistor M1, develops across the detection resistor RS. The detection voltage VCS is input to a current detection terminal (CS terminal) of the control circuit 100r. The control circuit 100r is configured to control, based on the detection voltage VCS, the current ILp that flows through the primary winding W1.
The feedback circuit 210 is configured to generate a feedback voltage Vfb that corresponds to the output voltage VOUT, and to supply the feedback voltage Vfb thus generated to a feedback terminal (FB terminal) of the control circuit 100r. The feedback circuit 210 includes a shunt regulator 212 and a photocoupler 214. The shunt regulator 212 is configured as an error amplifier, and is configured to generate a feedback signal S11 having a level adjusted such that the difference between the output voltage VOUT and a predetermined target value approaches zero, and to supply the feedback signal S11 thus generated to a light-emitting diode of the photocoupler 214. A phototransistor (or otherwise a photodiode) of the photocoupler 214 is configured to convert a light signal S12 received from the light-emitting diode into the feedback voltage Vfb that corresponds to the feedback signal S11.
On the primary winding side, the transformer T1 includes an auxiliary winding W3, in addition to the primary winding W1. The auxiliary winding W3, a second diode D2, and a second output capacitor CVCC form a second DC/DC converter. At the second output capacitor CVCC, a DC voltage Vcc develops according to the switching of the switching transistor M1. The DC voltage VCC is supplied to a power supply terminal VCC (VCC terminal) of the control circuit 100r. A start resistor Rstart is arranged between the VCC terminal and the input terminal P1. In the starting operation, the capacitor CVSS is charged via the start resistor Rstart, thereby supplying the power supply voltage VCC to the control circuit 100r. 
The control circuit 100r is configured as a so-called peak current mode pulse modulator. Specifically, the control circuit 100r includes an edge blanking circuit 102, a pulse modulator 110, a driving circuit 130, and a light load detection circuit 140.
Immediately after the switching transistor M1 is turned on, the detection voltage VCS temporarily jumps. In order to prevent undesired turning-off of the switching transistor M1 due to such a jump in the detection voltage VCS, the edge blanking circuit 102 is configured to mask the detection voltage VCS during a mask period immediately after the switching transistor M1 is turned on.
A capacitor Cfb is connected to an FB terminal as an external component. Furthermore, the FE terminal is pulled up via a resistor R11. The feedback voltage Vfb is divided by means of the resistors R12 and R13.
The pulse modulator 110 is configured to generate a pulse signal SPM having a duty ratio which is adjusted according to the feedback voltage Vfb. The pulse modulator 110 is configured to control the timing at which the switching transistor M1 is turned off, according to the detection voltage VCS which is proportional to the coil current ILp that flows through the switching transistor M1. Known examples of such a pulse modulator 110 include an average current mode modulator, a peak current mode modulator, and a fixed off-time mode pulse modulator. A driver 104 is configured to perform switching of the switching transistor M1 according to the pulse signal SPM.
The pulse modulator 110 shown in FIG. 1 is configured as a peak current mode modulator, and includes an error comparator 112, an oscillator 114, and a logic unit 116. The error comparator 112 is configured to compare a divided feedback voltage Vfb′ with a detection voltage VCS′. The error comparator 112 is configured to generate an off signal SOFF which is asserted when the detection voltage VCS′ reaches the feedback voltage Vfb′.
The oscillator 114 is configured to generate an ON signal SON which is asserted with a predetermined cycle. The logic unit 116 is configured as an SR flip-flop. The logic unit 116 is arranged such that the ON signal SON is input to its set terminal, and an OFF signal SOFF is input to its reset terminal. An output signal (which will be referred to as a “pulse modulation signal”) SPM of the logic unit 116 transits to the on level (high level) that corresponds to the on state of the switching transistor M1 every time the ON signal SON is asserted. Furthermore, the pulse modulation signal SPM transits to the off level (low level) that corresponds to the off state of the switching transistor M1 every time the OFF signal SOFF is asserted.
The driving circuit 130 is configured to perform switching of the switching transistor M1 according to the pulse signal SPM. The driving circuit 130 includes a pre-driver 132 and a driver 134.
The light load detection circuit 140 is configured to detect a light load state in which the DC/DC converter 10r outputs a reduced output current. The light load detection circuit 140 is configured to generate a light load detection signal S140 which is asserted (set to low level) when the DC/DC converter 10r enters the light load state. The light load detection circuit 140 includes a burst comparator 142 and an inverter 144.
When, in the light load state, the output current of the DC/DC converter 10r falls, the output voltage VOUT rises, and the feedback voltage Vfb drops. Thus, the burst comparator 142 is configured to compare the feedback voltage Vfb′ with a predetermined threshold voltage Vth. Furthermore, the burst comparator 142 is configured such that, when Vfb′ becomes smaller than Vth, it judges that the DC/DC converter 10r has entered the light load state. The inverter 144 is configured to invert the logic level of the light load detection signal S140.
The pre-driver 132 is configured to suspend the switching of the switching transistor M1 during a period in which the light load detection signal S140 is asserted.
In the heavy load state, the DC/DC converter 10r shown in FIG. 1 operates at a switching frequency that is the same as the frequency of the ON signal SON generated by the oscillator 114. Typically, the frequency of the ON signal SON is set to a frequency that is sufficiently higher than the audible band. For example, the frequency of the ON signal SON is set to a frequency on the order of 50 to 100 kHz.
In the light load state, the switching transistor M1 performs a burst switching operation according to the light load detection signal S140. In this state, the switching rate of the switching transistor M1 is reduced. This reduces the charge/discharge current that flows to/from the gate capacitance of the switching transistor M1, thereby providing improved efficiency.
With such an arrangement, the period in which the light load detection signal S140 is asserted in the light load state, i.e., a period in which the switching operation is suspended, becomes longer as the supply of electric power to the load becomes smaller. Thus, in the light load state, the effective switching frequency of the switching transistor M1 becomes lower as the period of suspension of the switching operation becomes longer, and at length it enters the audible band, which is equal to or below 20 kHz, leading to acoustic noise. In particular, such acoustic noise ranging between 4 kH and 20 KHz is also referred to as “mosquito noise”, which is very unpleasant. Thus, there is a demand for reducing such acoustic noise.
Also, the length of the switching noise suspension period, i.e., the switching frequency in the light load state, depends on the capacitance of the capacitor CM and the input voltage VH, in addition to the electric power supplied to the load. The capacitance of the capacitor CM and the input voltage VH differ according to the platforms on which the control circuit 100r is operated. Thus, it becomes necessary to provide noise countermeasures according to the platform.